1) Field of the Invention
The present invention relates to a semiconductor device having an interlayer contact structure, and to a process for producing the semiconductor.
2) Description of the Related Art
In the complementary MOS (Metal Oxide Semiconductor) field effect transistors (CMOSs) constituted by an n-channel MOS field effect transistor (nMOS) and a p-channel MOS field effect transistor (pMOS), it is desirable to increase the carrier mobility in each of the nMOS and pMOS transistors in order to speed up the nMOS and pMOS transistors.
According to a conventional technique for increasing the carrier mobility, silicongermanium (SiGe) is used in a layer underlying a Si-channel region, or in source and drain regions sandwiching the Si-channel region. In another conventional technique (disclosed, for example, in Japanese Unexamined Patent Publication No. 2005-057301), predetermined films (for example, films having predetermined thicknesses or predetermined areas) are formed over transistors so as to apply stresses to channel regions in the transistors, where the stresses are determined according to the predetermined films.
Generally, tensile stress in the channel region is effective in increasing the mobility of electrons, and compressive stress in the channel region is effective in increasing the mobility of positive poles. In the CMOSs structures, the carrier mobility in the nMOS substructure (e.g., nMOS transistor) and the pMOS substructure (e.g., pMOS transistor) can be respectively increased by forming a film which applies tensile stress to the nMOS substructure, and a film which applies compressive stress to the pMOS substructure.
However, in the structures in which films (stressing films) for respectively applying predetermined stresses to channel regions in the nMOS substructure and the pMOS substructure are formed, problems occur as explained below.
Before the problems are indicated, a process for forming different stressing films over the nMOS substructure and the pMOS substructure constituting a CMOS converter circuit (as an example of a semiconductor device constituted by an nMOS substructure and a pMOS substructure) is explained below.
FIGS. 35 to 41 are schematic cross-sectional views of an essential portion of a CMOS structure, and presented for showing an example of a process for forming stressing films, where FIG. 35 shows the essential portion in a stage before formation of the stressing films, FIG. 36 shows a stage in which a first etching stopper film is formed, FIG. 37 shows a stage in which a first stressing film and a second etching stopper film are formed, FIG. 38 shows a first etching stage, FIG. 39 shows a stage in which a second stressing film and a third etching stopper film are formed, FIG. 40 shows a second etching stage, and FIG. 41 shows a stage in which an interlayer insulation film is formed.
In the first stage in the process for forming the stressing films, as illustrated in FIG. 35, the CMOS structure 100 containing an nMOS substructure 120 and a pMOS substructure 130 is formed as a basic structure on a Si substrate 101. In the CMOS structure 100, element isolation of the nMOS substructure 120 and the pMOS substructure 130 is realized by the trenches 102 arranged for shallow trench isolation (STI). In the Si substrate 101, a p-well 121 is formed in the vicinity of the nMOS substructure 120, and an n-well 131 is formed in the vicinity of the pMOS substructure 130. The boundary between the p-well 121 and the n-well 131 is located approximately in the middle between the nMOS substructure 120 and the pMOS substructure 130.
A gate electrode 104 common to the nMOS substructure 120 and the pMOS substructure 130 is arranged over the nMOS substructure 120 and the pMOS substructure 130 through a gate insulation film 103, and side walls (not shown) are formed on the sides of the gate electrode 104. In addition, source and drain regions (not shown) are formed in the Si substrate 101 on both sides of the gate electrode 104. Further, a region 105 of a silicide of cobalt (Co), nickel (Ni), titanium (Ti), or the like is formed over the gate electrode 104. Although not shown, silicide regions are also formed over the source and drain regions as well as the gate electrode 104.
After the CMOS structure 100 having the above basic structure of FIG. 35 is formed, a film of silicon oxide (SiO2) having a thickness of approximately 10 nm is formed as the first etching stopper film 106 by using TEOS (tetraethylorthosilicate), as illustrated in FIG. 36.
Then, as illustrated in FIG. 37, a film of silicon nitride (SiN) being designed for application of tensile stress and having a thickness of approximately 80 nm is formed as the first stressing film 107 over the layered structure of FIG. 36. In addition, a film of SiO2 or the like having a thickness of approximately 20 nm is formed as the second etching stopper film 108 on the first stressing film 107. The second etching stopper film 108 is used as a hard mask in the first etching step, which is explained later. Alternatively, it is possible to dispense with the formation of the second etching stopper film 108.
After the first stressing film 107 and the second etching stopper film 108 are formed, in the first etching step, a portions of the first stressing film 107 and a portions of the second etching stopper film 108 formed over the pMOS substructure 130 are removed by etching. After the first etching step, the first stressing film 107 and the second etching stopper film 108 remain over only the nMOS substructure 120 as illustrated in FIG. 38.
Subsequently, as illustrated in FIG. 39, another film of silicon nitride (SiN) being designed for application of compressive stress and having a thickness of approximately 80 nm is formed as the second stressing film 109 over the layered structure of FIG. 38. In addition, a film of SiO2 or the like having a thickness of approximately 20 nm is formed as the third etching stopper film 110 on the second stressing film 109. The third etching stopper film 110 is used as a hard mask in the second etching step, which is explained later. Alternatively, it is possible to dispense with the formation of the third etching stopper film 110.
After the second stressing film 109 and the third etching stopper film 110 are formed, in the second etching step, the portions of the second stressing film 109 and the third etching stopper film 110 formed over the nMOS substructure 120 are removed by etching. After the second etching step, the second stressing film 109 and the third etching stopper film 110 remain over only the pMOS substructure 130 as illustrated in FIG. 40. In the structure illustrated in FIG. 40, the portion of the first stressing film 107 remaining over the nMOS substructure 120 and one of the trenches 102 which is located between the nMOS substructure 120 and the pMOS substructure 130, and the portion of the second stressing film 109 remaining over the pMOS substructure 130 and the one of the trenches 102 are not apart from each other and do not overlap with each other. That is, the above portion of the first stressing film 107 and the above portion of the second stressing film 109 abut each other at the position vertically above the boundary between the p-well 121 and the n-well 131.
In the above process, the second stressing film 109 for application of compressive stress is formed after the first stressing film 107 for application of tensile stress is formed. Alternatively, it is possible to form the first stressing film 107 for application of tensile stress after the second stressing film 109 for application of compressive stress is formed and the patterning and etching are performed.
After the structure illustrated in FIG. 40 is formed, a film of SiO2 or phosphosilicate glass (PSG) having a thickness of approximately 370 nm is formed over the structure of FIG. 40, as illustrated in FIG. 41. Thereafter, a contact hole which extends through the interlayer insulation film 111 to the depth of the silicide region 105 is formed, and then the contact hole is filled with a predetermined material for electrode, so that a contact electrode is formed.
FIGS. 42 and 43 are schematic cross-sectional and plan views of a first example of the essential portion of the CMOS structure. In FIGS. 42 and 43, the contact-hole formation region (in which the contact hole is formed) is indicated by dashed lines. In FIG. 43, the interlayer insulation film 111 and the first and second etching stopper films 106 and 108 are not shown.
According to the normal design, as illustrated in FIGS. 42 and 43, the contact-hole formation region 112 (in which the contact hole extending to the silicide region 105 is formed) is arranged in such a manner that the center of the region 112 is located approximately vertically above the boundary between the first stressing film 107 and second stressing film 109, i.e., the boundary between the p-well 121 and the n-well 131. In FIGS. 42 and 43, the boundary between the p-well 121 and the n-well 131 is indicated by the dashed line Q.
However, in the case where the contact hole is formed in the contact-hole formation region 112 as above, according to the aforementioned process for forming the stressing films, the thickness of the second stressing film 109 at the bottom of the contact hole is approximately twice the thickness of the first stressing film 107 as illustrated in FIG. 42. Therefore, if the near-bottom portion of the contact-hole formation region 112 is simply etched, according to the properties of the first and second stressing films 107 and 109, overetching for exposing the silicide region 105 becomes insufficient in the thick portion of the second stressing film 109 even when the overetching for exposing the silicide region 105 is sufficient in the first stressing film 107. In such a case, it is possible to cause overetching sufficient to remove the thick portion of the second stressing film 109. However, when etching which causes overetching sufficient to remove the thick portion of the second stressing film 109 is performed, the portion of the silicide region 105 located under the bottom of the contact-hole formation region 112 (in particular, the portion of the silicide region 105 located under the first stressing film 107) is prone to etching damage, which can cause problems such as increase in the resistance.
Although the first and second stressing films 107 and 109 abut each other in the example illustrated in FIGS. 42 and 43, in practice, the first and second stressing films 107 and 109 can partially overlap, or a gap may be produced between the first and second stressing films 107 and 109.
FIG. 44 and FIG. 45 schematic cross-sectional views of second and third examples of the essential portion of the CMOS structure in each of which a contact-hole formation region is indicated. In FIGS. 44 and 45, the same elements as FIGS. 42 and 43 bear the same reference numbers as FIGS. 42 and 43.
In the second example illustrated in FIG. 44, a portion of the second stressing film 109 overlaps the first stressing film 107 (which is formed before the second stressing film 109) at the bottom of the contact-hole formation region 112. In the third example illustrated in FIG. 45, a gap is produced between the first and second stressing films 107 and 109 at the bottom of the contact-hole formation region 112. The above overlapping or the gap is caused by misalignment in patterning for formation of the first and second stressing films 107 and 109. In practice, one or a mixture of the situations illustrated in FIGS. 42, 44, and 45 can occur at the bottom of the contact-hole formation region 112.
For example, consider a case where the contact-hole formation region 112 containing the arrangement illustrated in FIG. 44 or 45 is etched under an etching condition designed for the arrangement illustrated in FIG. 42 in which the edges of the stressing films 107 and 109. The etching under the above etching condition cannot realize sufficient overetching in the region in which the first and second stressing films 107 and 109 overlap, so that the opening formed by the above etching becomes insufficient for being the contact hole. In particular, in the case where a portion of the second etching stopper film 108 is formed over the first stressing film 107, the opening formed by the above etching is more likely to be insufficient. On the other hand, in the case where a gap is produced between the first and second stressing films 107 and 109 at the bottom of the contact-hole formation region 112, the silicide region 105 exposed in the gap or the gate electrode 104 underlying the silicide region 105 can be damaged by excessive overetching.
As explained above, in the case where predetermined stressing films are dividedly formed over the nMOS substructure and pMOS substructure constituting a CMOS structure, and a contact hole is formed through the boundary between the stressing films, etching damage can occur in conductive regions such as a silicide region or a gate electrode located under the contact hole, or the contact hole (which extends to the conductive regions) can be imperfectly formed, so that the resistance increases or electric connection failure can occur.